TransEDA is the leader in Verification Closure Measurement solutions for electronic designs – securing a faster and safer path to verification closure.
Unique functionalities such as comprehensive assertion coverage, coverability analysis, specification coverage with engineering change impact analysis, and automatic bus protocol checking, enhance traditional code coverage, test suite optimization, HDL rule checking and static assertion checking capabilities to form an integrated Verification Closure Management solution. Other products include verification IP with bus-based system-level test automation and transistor-level functional abstraction.
Assertain – The Next Generation Verification Closure solution
Delivering, in a single environment, total measurement and control of the digital design verification process.
- Coverability Analysis – Advanced Code Reachability Determination
- VN-Check – Configurable HDL Checking
- VN-Cover – Coverage Analysis
- VN-Cover Emulator – Coverage Analysis for HW Emulation
- VN-Optimize – Test Suite Analysis & Optimization
- VN-Control – System-Level Test Automation
