There are three fundamental stages in Assertain: a static stage, a dynamic stage and the verification closure stage. Assertain HDL follows the same scheme, described below:
When a design is first read, customizable static rules are automatically verified on the RTL files. This includes not only common lint such as syntax and semantic checking, but also complex rules about design and coding style, naming conventions, documentation, etc. In addition, automatic formal rule checking can be performed on user’s choice to exhaustively verify the structural consistency of various design constructs such as FSMs, busses, pragmas, arrays, etc.
When the static checks are clean, engineers start their dynamic simulation with Assertain HDL monitoring code coverage information using the industry’s most comprehensive and accurate set of metrics. Recorded coverage is displayed in the user-friendly GUI to provide critical feedback on how good the test suite exercises the design. Tests grading and optimization can then be used to extract the most efficient regression test suite, from the code coverage point of view.
When coverage reaches a point close to the sign-off target, it is time to identify and focus on insufficiently tested areas to perform verification closure. Assertain HDL enables users to run coverability analysis on remaining uncovered items in order to get a more accurate view of what is coverable and what is not, in order to speed up the convergence process.