Key Features

Static verification phase – Key Features

  • A fully user configurable verification set-up to enforce a consistent verification strategy
  • One single data entry point, regardless of the mix of languages used – VHDL, Verilog and SystemVerilog
  • A complete set of pre-packaged rule-sets including RMM, synthesis, DFT, language portability, and best practices
  • Advanced formal-based rule checks that complement standard linting rules:
    • FSM safety and liveness (state and transition reachability, deadlock and livelock check)
    • Synthesis pragma violations (full case, parallel case)
    • Bus contention and high impedance detection
    • Array index out-of-bounds

Dynamic verification phase – Key Features

  • A unified coverage results database for consistency across the entire project
  • The widest range of code coverage metrics – statement, branch, condition, path, toggle, trigger, signal trace, FSM state, arc and path
  • Highest capacity test suite optimization based on code coverage results, linking RTL code to test benches to speed-up ECO iterations
  • Code coverage capabilities on Eve Zebu and Cadence Incisive Xtreme emulators/hardware acceleration platforms

Verification closure phase – Key Features

  • Global coverage and rule checking dashboard view, with data filtering and customizable thresholds and sign-off criteria
  • Unique coverability analysis facilities of design branches and expressions using TransEDA’s Focused Expression Coverage (FEC) technology and stat-of-the-art formal engine
  • Automatic user-qualified filtering of unreachable coverage items for faster convergence to coverage sign-off

Miscellaneous Features

  • Graphical and command line interface for interactive or batch mode operation
  • Easy integration into any existing design flow
  • Full backwards compatibility with existing TransEDA tools and results files allowing a smooth and seamless up-grade path

Assertain Packaging

Assertain is shipped in three different versions:

  • HDL – Entry-level configuration for extensive HDL static verification and code coverage measurement
  • ABV – HDL version plus full support for assertion-based verification facilities and design coverability analysis
  • VCM – ABV version plus requirements traceability, full coverability analysis and formal assertion checking for total Verification Closure Management


Assertain is available now. The tool is supported on the following platforms and operating systems:

  • SUN Solaris 7, 8 and 9
  • Red Hat Enterprise 3.0
  • Red Hat Linux 8
  • Microsoft Windows 2000 and XP

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