Design teams obtain the highest value from VN-Check when they use it from the beginning of the design process to find design errors fast. Catching and fixing bugs at this early stage in the design development ensures swift and smooth progress through the remainder of the design and verification flow.
Catch a Large Spectrum of Bugs
VN-Check provides a wide variety of checks to eliminate early design problems that cause downstream errors and make debug long and painful. Among the checks are the following:
- Syntax and semantic checks that ensure compliance with VHDL (IEEE 1076-1993) and Verilog (IEEE 1364/OVI 1.0, 2.0) HDL language standards and with SystemVerilog 3.1
- Coding checks that analyze the HDL for simulation, synthesizability, design-for-reuse, and testability requirements
- Design practice checks that include hierarchy, combinatorial loops, reset/clocking styles, clock domain crossing synchronisation and many more
- Advanced rules option that performs deeper formal analysis of design consistency
- Style, documentation and naming checks that ensure adherence to user-defined coding guidelines
- Compliance checks with FPGA design flow requirements
- Assertions density rules that guides on correct assertion usage
VN-Check is easy to use from the command line or its graphical user interface. Simply select the rule-sets, the HDL source files, specify any options and the tool checks the code and generates a results report. Once the verification is finished, VN-Check’s Results Navigator enables unprecedented results presentation capabilities. Display the results by source file, module, or rule-set. The summary window highlights a brief, high-level view of the design status; the detail window provides information via customizable columns on each individual violation with cross-referencing to the source code.
Define, Configure and Organise the Rules
VN-Check provides the flexibility needed to adjust rules to match requirements on a per-run basis. Rules can be configured with parameters like pre-defined values, user-defined integers or strings, or regular expressions. The violation severity can be set to three different levels; in addition the user can create custom violation messages to provide clear, concise feedback.
VN-Check allows fine grain control of the design rules, providing maximum efficiency and flexibility. This detailed control prevents designers from becoming overwhelmed with irrelevant violation messages. Rules can be regrouped into custom rule-sets that meet company or team standards. These rule-sets can be multiply selected to check against several styles, they can also be published for use by distributed design and verification team members, ensuring company-wide, high quality code.
VN-Check is supplied with the following rule-sets:
Reuse Methodology Manual (RMM)
Checks from the Reuse Methodology Manual including coding rules and guidelines for reuse, maintainable, portable code.
Checks and weightings that measure your code against the OpenMORE standard.
Checks for compliance with the requirements of logic synthesis tools to achieve fault free synthesis runs.
Verilog-VHDL and VHDL-Verilog
Checks for portability rules between VHDL & Verilog languages.
DFT and FSM
Design for Test and FSM rule-sets are supported.
Checks that represent generally accepted good HDL coding practices.
Guides designers toward an optimal use of assertions in their RTL code.
Advanced Rule Options
Collection of advanced rules for design consistency checking includes:
- FSM safety and liveness (state and transition reachability, dead lock)
- Synthesis Pragma violations (full case, parallel case)
- Array index out-of-bounds
- Bus contention detection
- Deterministic initialization (minimal number of cycles until circuit is stable at reset)