Coverability analysis formally determines whether or not currently uncovered code in a HDL model can be reached. If so, engineers need to enhance the test bench to cover this code. They can then leverage the stimuli information from the VCD file provided by the tool. If not, the reason for the item being uncoverable must be understood, and the item is filtered from the final results to reflect more realistic coverage ratios.
TransEDA’s Coverability analysis tool can be applied to branches, to combinations of FEC (Focused Expression Coverage) terms in expressions that control conditional statements, and to those that appear in assignments.
Why perform Coverability Analysis?
Coverability Analysis helps engineers to achieve their coverage goals faster. These goals may sometimes not be attainable because:
- The model being tested contains dead code, unreachable by any test, that can result from a designer mistake or more frequently be part automatically generated code
- The uncovered code is included for test purposes, or for compatibility with synthesis tools, and is not exercisable
- The uncovered code belongs to an IP module that is used in such a way that part of its functionality has been disabled on purpose
- There are errors or redundancies in the HDL representation
Pin point and filter unreachable code
As seen above, unreachable code can be the consequence of a bug in the RTL code or of unexpected redundancies in complex expressions, for example. In this case, coverability analysis unambiguously highlights the bug and the designer needs to fix the code.
On the opposite, the presence of unreachable but expected code can significantly decrease the overall coverage percentage, sometimes making the sign-off goals impossible to attain. In this scenario, the uncoverable parts must be excluded so that they do not influence the overall results. Coverability analysis automatically performs this filtering, independent of the test bench so that the filtering information lives with the design.
In both cases, coverability analysis prevents the verification engineer from spending considerable time looking for a test sequence that does not exist.
Coverability analysis provides help with reachable code
On the other hand, the code may be reachable but has not been covered because the applied test is not comprehensive enough. It is then an engineering task, and most often a long and difficult one, to work on the test bench in order to increase the design coverage.
Coverability analysis helps the engineer in this task by providing an illustration of how a given branch or sub-expression can be covered. This information is given in a form of either a VCD file, or a VHDL or Verilog testbench, and if an accurate environment has been specified to the tool, the covering test sequence generated by coverability analysis is fully functional.
The Coverability Analysis process
TransEDA’s coverability analysis tool uses formal techniques to prove, with mathematical certainty, that branches and focused sub-expressions are either coverable or not. Analysis can be performed either globally or on user-selected branches and FEC terms.
The reachability problem is then automatically expressed as assertions, transparently fed to an embedded formal engine that reports back the coverability status for these items.
Coverage percentages are then recomputed to eliminate unreachable items, and VCD or test bench files are created to guide the user on how to exercise the coverable code constructs.