VN-Cover offers an extended set of user-selectable code coverage metrics including:
- Statement and branch coverage, which provide a quick indication of verification progress
- Condition and path coverage, which are crucial in situations where there are complex terms in branches or where there are consecutive decision blocks
- Toggle coverage, which identifies signals that have been inactive during a simulation
- Triggering coverage, based on the examination of the sensitivity lists in VHDL constructs
- Variable and signal trace coverage, useful for checking coverage of vector-based HDL representations
VN-Cover also offers a very comprehensive set of FSM coverage measurements including; state, arc and path coverage. It also reports any terminal and unreachable states.
Having automatically detected and extracted any state machine from your Verilog or VHDL source code, VN-Cover automatically generates a state diagram to help identifying any FSM coverage problems.
Enhanced Accuracy with Deglitch Capability
Using coverage metrics to determine simulation completeness requires that the code coverage be very accurate.
For this purpose, VN-Cover provides a unique feature that enables filtering out false coverage information caused by simulation glitches. A line, statement or branch can be temporarily traversed when the simulator updates its event queue in a delta delay. This is a transient state that should not increment the coverage count. Via its Deglitch capability, VN-Cover is able to detect and suppress all transient coverage information, hence eliminating false positive coverage from the final calculation and report.
Coverability Analysis Option
To increase code coverage accuracy even further, unexercisable parts of the HDL code have to be detected and then filtered out.
VN-Cover’s Coverability Analysis option guides the user through this complex task. This option automatically invokes formal techniques to check for reachability in any uncovered branches or expression terms of the code. Analysis can be performed either globally or on user-selected items: lines or FEC terms. When uncoverable HDL parts have been found, they are highlighted and a FEC’s diagnostic report list all unreachable terms of the expression. Coverage measurements are then recomputed to reflect the updated numbers of coverable items.
Test-suite optimization is a powerful functionality for identifying the minimum set of test benches in a suite that give maximum coverage in the shortest run-time. Run-time savings can often reach 90% or more.
VN-Cover includes a bounded version of this feature. Full test optimization capability is available with the VN-Optimize tool.
VN-Cover generates coverage reports, detailed summaries, project summaries and sign-off reports in either plain text or in HTML format. Text reports are a useful way to document verification progress in a project-history folder. HTML-based reports are the ideal way of sharing information with other project team members via an Intranet or the Internet.