Industrial Partners

Altera Access Program
Assertain enables first-class coverage and verification with Atera’s FPGA’s.
cadence.gif Cadence Connections Program
Assertain, VN-Cover and VN-Cover Emulator enable first class coverage for dynamic verification performed with Incisive Unified Simulator (NC-series) and Incisive Palladium accelerators/emulators.
Assertain and VN-Cover also link to Specman Elite, SpeXsim and SpeXtreme via CAI to provide industry’s most accurate code coverage solution to drive test generation.
eve.gif VN-Cover Emulator / ZeBu interface
VN-Cover Emulator seamlessly integrates with Zebu (Zero Bug) system to provide code coverage for hardware emulated designs.
mentor.gif Mentor Graphics OpenDoor Program
Assertain, VN-Cover and VN-Cover Emulator raise code coverage to its highest level when used with vStation and Celaro emulators and with the ModelSim simulator.
novas.gif Novas Harmony
imPROVE-HDL and imPROVE-HPK formal results can be debugged in Debussy’s environment using our specific link to Novas’ flagship tool.
Sonics Inc
Assertain and TransEDA’s Coverability Analysis tool speed up the convergence toward coverage sign-off criteria of Sonics’ SMART SoC interconnect products. imPROVE-HPK ensures the compliance of Sonics’ interconnect IP with the OCP protocol.
synopsys.gif Synopsys Catalyst Program
Assertain and VN-Cover provide state-of-the-art code coverage metrics to VCS users.


EDA Organizations

accellera.gif Accellera
dandr.gif Design and Reuse
edacon.gif EDA Consortium
ocp.gif OCP-International Partnership
pcisig.gif PCI SIG
sysver.gif SystemVerilog

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