Assertain-ABV is a complete Coverage and Design Checking solution that:
- Quantifies verification completeness using the most comprehensive and accurate set of code FSM, assertion and functional coverage metrics
- Screens RTL code using extensive rule checking capabilities completed by automatic formal analysis
- Cuts weeks off the verification schedule by deploying an embedded formal engine to perform coverability analysis
- Straightforward to integrate into existing verification flows as the tool works with all leading simulators
- Allows easy management and visualization of verification closure criteria in a single, coherent environment
- Links specifications, assertions, RTL code and test benches using unique requirements traceability technology
Assertain is an innovative environment dedicated to measuring the completeness of the verification of digital SoC designs, in order to secure a faster and safer path to verification closure.
Covering all front-end design stages from original text specification through to validated RTL, Assertain monitors, measures and helps manage the verification process in one integrated environment. The tool seamlessly brings together rule, protocol and assertion checking; code and assertion coverage; design and assertion coverability analysis; test suite optimization; and specification coverage using proven requirements traceability techniques.
Assertain exists in three versions, each of them corresponding to a well defined type of application. Assertain ABV has been designed to closely monitor assertion-based verification flows by using TransEDA’s unique assertion coverage metrics, among which the newly introduced assertion step and variable coverage. This version includes all Assertain HDL features, and extends them with advanced rule checking, design coverability analysis and dynamic assertion coverage measurement. Assertain ABV allows engineers to get the most complete and accurate view of how well their tests exercise the RTL code, the assertions and the coverage points.